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Readme - Compact flash monitor/debug demonstration2 w/ ~4 ? k) x5 C' B
GENERAL DESCRIPTION:
1 Z2 ~1 J- n: C9 JThis distribution contains hardware and software examples suitable for
# r, e2 r6 Y0 B3 @! }5 H! ooperation of the the Compact Flash interface (True IDE mode) peripheral
9 Y$ H- A) e/ w0 f. qincluded in the Nios II 5.0 development kit. This peripheral's register
- i7 p4 {3 h4 ]* amap is equivalent to the compact flash interface previously posted to the 6 ?" w) d# X8 g1 R/ \6 ?
www.niosforum.com "Tested IP" area by Microtronix. 0 x3 u( ~- N; [( X
HARDWARE EXAMPLE DESIGNS / X2 d G/ H/ R, @" N$ L
Included with this distribution are several hardware example designs
0 P7 Y# S' q! F) j5 ]6 d- nillustrating how to connect Compact Flash pins to the I/O exported from
3 d% w+ \' G x& `- f# Y7 pthe peripheral. The examples supplied are pre-built and tested on the# H3 m3 b8 s' @4 o2 ^ x8 I
following development boards:5 j# h& }, H. Y. [
- Nios Development Board, Cyclone Edition (EP1C20)1 G* I/ |8 x6 B" Z# a
- Nios Development Board, Cyclone II Edition (EP2C35)& }6 a+ W' _$ Q! t9 |0 J$ o U& F' L& T
- Nios Development Board, Stratix Edition (EP1S40)/ i( [( ]. Q( ]2 \ Z
- Nios Development Board, Stratix II ES Edition (EP2S60ES)/ I0 X8 D- M6 e! x) o; t
5 a) j6 q; a# `6 h: f( `1 ]8 \
For users of the Nios Development Board, Stratix Edition (EP1S10 or EP1S10ES/ C* Q0 y) u- e4 \ L
Altera devices), it is suggested that you start with the EP1S40 example design
0 k- g) ]( ?. @8 c1 Vand change SOPC Builder board component & Quartus device assignment, and then- w4 g8 p* ], V; J: z
re-compile the design. Do not remove I/O assignments; the I/O assignments for & n0 Q! {0 f. i) f3 _ _& a
these three development boards are identical.6 F0 k6 G& Y8 R
In addition, the the Quartus project setting (.qsf) files included with each of
3 ?4 g+ B F9 Y) P& nthe above hardware examples includes pin-assignments for Compact Flash that you
! \8 z- ^. R3 y* ]& {( cmay easily copy to your own custom design that uses Compact Flash.
: o+ s* o. z) {2 mNote: Hardware example designs in Nios II 5.0 included these same pin : i& ~4 J7 j4 i( A+ s4 Q2 h
assignments in each design.# g+ L+ E' d/ Q; E. P K4 l' E9 N
SOFTWARE EXAMPLES
+ o9 J: S3 O$ k& o, O1 L$ `8 _The software included in this package allows rudimentary IDE access to( o! O, l4 X3 @7 M( I" T- H! c; r5 j
Compact Flash, including debug routines, hot-swap capability, and
F1 ?& l1 R4 r/ i) \% h+ Bthe ability to read/write compact flash in either LBA or CHS addressing
% U. `' @) J* u" _modes. No file system support is provided, though this example would
3 f" l& }6 e) Userve as a fine starting-point for a higher-level file-system interface.
; |9 Y& R# ?( m# F8 X6 R5 q6 N+ u9 P: pAdditional software support for the Compact Flash interface is included: U0 }3 I1 D# ~) y- L7 q; c
in the eCOS release for Nios II 5.0, and Micrium MicroC/FS file system,
& B( P. `' c' Y ] ?both of which have been tested with the Compact Flash interface
% e w! v) _7 `( y/ Q8 S% F+ Uperipheral. These software interfaces do NOT require the software included' B0 v- F" }/ f% u
with distribution, but may be used with the hardware example designs
) X6 C5 {& p5 d0 Uincluded with this distribution.! r! D5 D) p) C, g0 g% S8 q
To build the software example design, open the Nios II IDE, create a new Nios 7 L7 \/ S% V! {& A) w2 e; x7 p
II C/C++ application (it is suggested that you start with a template such as
) {4 g; F6 j: f"Hello World" or "Blank Project"), then, copy the source-files to the newly 9 ]9 ]1 w4 ]: r5 m3 [6 m
created project directory and "refresh" the project contents in the IDE (F5).1 F7 }- V6 v# X5 A+ z: m
Following this, you may build the application. The main() routine is located& x, U4 P" p7 Z* x0 a7 {7 t
in file cf_test.c
2 y1 d( p4 N2 iNote: If you start with hello world, be sure to remove hello_world.c to prevent
: g7 H f- v# i2 rconflicts during compilation.5 f) ~: P# L; E6 G7 @* z5 Q4 s
REQUIREMENTS:
* [0 G3 i" f0 ^2 R% V( C, n( D3 s7 RThe example software requires an altera_avalon_cf peripheral named "cf"
% F9 H: M+ [, X2 ?( [. R; |! k% Oinstantiated in your SOPC Builder design. In addition, the default LCD . j1 v7 x; F( x# m6 e& o+ S# ?9 Q
interface that is included in "standard" and "full_featured" Nios II example x, } H! v+ j/ D) |
designs may not be used, as it shares pins with the compact flash socket.
5 H9 c. f/ Z/ B3 M; r+ B" } B& IThe hardware example designs included with this distribution conform to the
, z' ~$ U# _3 h6 X' E& U# O+ Oabove requirements.
' ^/ N F4 h. v, X" P7 }KNOWN ISSUES & WORKAROUNDS:
2 u$ }8 T3 w3 v8 uEvery effort has been made to make both the Compact Flash interface peripheral
, m5 R, Z+ ?: Eand software examples perform without flaws. However, certain known issues5 K1 z; W$ B" P; v7 c
may prevent Compact Flash card access.
: e5 S; N& J6 |" mThe following are relevant excerpts from the Nios II 5.0 errata discussing
4 h* }/ S$ K- ^% ?* NCompact Flash:8 {; j5 b$ Z7 J2 k# ?& p
- Intermittent failures while accessing Compact Flash card
3 [1 L" I, ~+ Y5 v 2 x ]3 U* _, E9 w: |
Nios II 5.0 includes a Compact Flash controller peripheral suitable for
6 m C. T" L/ ?9 W+ B( p4 @ interfacing to Compact Flash cards in True IDE mode on Nios development
! Z2 }# W+ D1 e6 q$ Y boards. In order for True IDE mode to operate, Compact Flash cards require ; P$ k" e3 {- Y' @' M* n) u
that the "ATASEL_N" input be driven to ground during power-up.
& Z2 m+ O* o$ [: V The Compact Flash controller peripheral includes a configurable power 4 ]& ~/ B+ P5 d# l" \0 t3 a
register used to power-cycle Compact Flash cards in Nios II software
! R d0 Y& @7 j* t) m+ D through a MOSFET on the Nios development boards. However, in certain 3 h! k9 j5 B) B
development boards, power to the Compact Flash card will not be turned b' T+ V3 S v' J( ?7 Y" Z
off completely during this power-cycle operation. Because of this, the
5 e# ~7 R! |. K1 [ "ATASEL_N" pin may not be sampLED during the power-cycle operation after 9 `4 r! ^+ U6 R8 h
FPGA configuration when this pin is driven to ground. Instead, "ATASEL_N"
8 N* b7 H/ a7 j6 m8 e4 I0 c& K( o may be sampled by the Compact Flash card when power is first applied to
+ C7 a }, w; o+ H/ \& X2 [* \2 a the development board, when I/O are not yet driven by the FPGA (before ) k( |# v& a! C
FPGA configuration).6 K# y2 h2 Y& v6 ^. E1 p" P6 Y
Workaround: If you encounter errors with Compact Flash when using the & w X2 \& F, P* U
Nios development boards, please try one of the following workarounds:
9 K1 O8 |$ U _1 A * Try a different Compact Flash card -- Certain cards are more 1 d+ C1 n1 H* l6 W; a
susceptible to the power-cycling issue than others.
3 a' Z; Z; `. v * Modify the Nios development board -- This is recommended for
* f9 | f* V6 z5 Q/ L8 V users who are familiar and comfortable with board-level
0 N2 A4 `& q! @& R, z; @ modifications. Disconnect pin 9 (ATASEL_N) on the Compact Flash ! M$ J4 l- l& W
socket on your Nios Development Board and tie this pin to ground. , A8 [" v Q9 @; s# {2 |8 I+ s
Note that the Compact Flash socket uses a staggered numbering on
1 P: I8 X5 ?% ^* Z1 o the pins (starting from pin 1: 1, 26, 2, 27, ...); please refer
5 q9 T! G1 G- W- k& _7 K to the Compact Flash Association specification for right-angle
, t' w; Z% n" H$ @9 e$ V. ~ surface-mount connectors for exact specifications on this connector. - N8 h, \% B: Z3 H" `
Caution: This will permanently enable True-IDE mode operation.
; R7 G U* Z$ d0 p. U% v8 I - Compact Flash card and LCD screen do not work concurrently
; e1 y& p+ L0 p$ X8 Q, n% D3 @ m If there is a Compact Flash card inserted in the development board, the ( m, I. t0 @$ R7 k5 D7 O- f+ m7 Z
LCD and other devices connected to the PROTO1 header might not work.
" _0 Y& K" ^* E7 p0 E Workaround: Remove the Compact Flash card to ensure proper operation of
8 |% o- q0 D( I the PROTO1 header, or vice versa.) U8 L8 _0 ^+ S
. _% F- o! d, x9 k0 ^: R
) ~ G1 @; B' _
在网上找到一个相当不错的CF控制器有兴趣可以研究一下 |
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