版主
主题
回帖0
积分10609
阅读权限200
注册时间2008-11-22
最后登录1970-1-1
在线时间 小时
|
Readme - Compact flash monitor/debug demonstration* `$ f: n8 ~/ t; A. ~6 z
GENERAL DESCRIPTION:7 ^: y5 c' n% T1 u. p+ }
This distribution contains hardware and software examples suitable for. F b# Y5 U! b d# @9 x
operation of the the Compact Flash interface (True IDE mode) peripheral
7 u' r( F6 V3 ?. x! k7 f* d5 ?. Pincluded in the Nios II 5.0 development kit. This peripheral's register ' p2 V# P7 ~: N
map is equivalent to the compact flash interface previously posted to the
6 z8 i O2 A5 B) ewww.niosforum.com "Tested IP" area by Microtronix. / f" Q o x* O/ O4 S
HARDWARE EXAMPLE DESIGNS * i8 z6 r* J3 _, D, I+ ~ i
Included with this distribution are several hardware example designs 0 j8 S1 V0 ?/ f5 z3 ?
illustrating how to connect Compact Flash pins to the I/O exported from
! M% k4 u' H" N# i* {- vthe peripheral. The examples supplied are pre-built and tested on the3 ]5 `$ y3 p J( l' J
following development boards:) \0 `( b- |1 _1 e6 a4 w
- Nios Development Board, Cyclone Edition (EP1C20)
! {, f6 c) q' n - Nios Development Board, Cyclone II Edition (EP2C35)
4 @7 U4 Z' n4 w- U1 P - Nios Development Board, Stratix Edition (EP1S40)) s3 U- \6 @- t
- Nios Development Board, Stratix II ES Edition (EP2S60ES)
3 }8 z/ {, M3 w7 o5 S
, L" s5 C. x5 S8 W x/ s% l$ hFor users of the Nios Development Board, Stratix Edition (EP1S10 or EP1S10ES
5 [ d P# z8 {" j1 y4 l! t. I( PAltera devices), it is suggested that you start with the EP1S40 example design
/ x, @, Y' W& wand change SOPC Builder board component & Quartus device assignment, and then* h5 v5 `0 b6 A: K i! P9 z3 C
re-compile the design. Do not remove I/O assignments; the I/O assignments for ' {' R* F% _6 }
these three development boards are identical.
9 D% J* r! p( _) E# R9 C- ~) kIn addition, the the Quartus project setting (.qsf) files included with each of" w$ b9 [5 \6 T1 {5 t1 @4 Z
the above hardware examples includes pin-assignments for Compact Flash that you , B6 V y# n( h9 f4 j
may easily copy to your own custom design that uses Compact Flash.
$ E5 l+ u9 d9 }# e- X4 J, I5 U& oNote: Hardware example designs in Nios II 5.0 included these same pin
- q$ w' g* S0 ~2 x" l& V- U5 o" q7 aassignments in each design.
: m+ e$ V, W5 \9 M4 N( nSOFTWARE EXAMPLES, N7 k2 T* x, z5 F9 e! w( l
The software included in this package allows rudimentary IDE access to0 `% i' ?' k: p/ D; _; [. \& _
Compact Flash, including debug routines, hot-swap capability, and * Y9 Q* _& U; f# A
the ability to read/write compact flash in either LBA or CHS addressing
- e# t7 O; j( h) a [; i; Omodes. No file system support is provided, though this example would
+ A% s! z( y9 c# O2 M0 Iserve as a fine starting-point for a higher-level file-system interface.3 U' s, E4 `; A: h+ ]
Additional software support for the Compact Flash interface is included/ S9 ]9 I# E3 a& l/ [9 y+ H. J; b3 ~
in the eCOS release for Nios II 5.0, and Micrium MicroC/FS file system,
: r9 v6 u0 a7 n5 rboth of which have been tested with the Compact Flash interface ! [% J1 S! c# }( \$ a
peripheral. These software interfaces do NOT require the software included) ~" i" ]/ K" `4 k0 Y( ?: i
with distribution, but may be used with the hardware example designs1 n6 t# P! b; m" u
included with this distribution.
- l0 V9 _ U- S0 KTo build the software example design, open the Nios II IDE, create a new Nios
6 J% d+ d0 H& ^& z' q! {! ZII C/C++ application (it is suggested that you start with a template such as
; `+ G Z% L* x# `"Hello World" or "Blank Project"), then, copy the source-files to the newly 9 W3 z% z ?! ^' T! l3 X
created project directory and "refresh" the project contents in the IDE (F5).
4 Q( `/ z9 B' pFollowing this, you may build the application. The main() routine is located4 D7 F$ |: c1 d+ I6 _! A/ j
in file cf_test.c* O5 e5 g' e& ^ `; _, o `& K
Note: If you start with hello world, be sure to remove hello_world.c to prevent
u) V6 X( O4 Dconflicts during compilation.
+ b! P6 F1 p: g! E+ g5 x; Q1 |REQUIREMENTS:# O# ~; R. r1 m0 a6 L
The example software requires an altera_avalon_cf peripheral named "cf" & [; A6 k8 K5 |# h
instantiated in your SOPC Builder design. In addition, the default LCD 5 }& }( K4 @9 H* Q
interface that is included in "standard" and "full_featured" Nios II example
t8 Z$ \! R& X' I# Adesigns may not be used, as it shares pins with the compact flash socket. : A+ |# L) {+ |
The hardware example designs included with this distribution conform to the
: ]. s: ]& B% V5 Q3 p) f+ dabove requirements.! L# j; }! `" V1 e4 [
KNOWN ISSUES & WORKAROUNDS:
0 Y$ S4 N1 y8 n% lEvery effort has been made to make both the Compact Flash interface peripheral( p. ~% T6 M+ w8 a
and software examples perform without flaws. However, certain known issues
6 f1 h K. Z8 a" ^) s3 D8 u5 Amay prevent Compact Flash card access. ( j$ {# L# n( `( @$ E6 v
The following are relevant excerpts from the Nios II 5.0 errata discussing
3 D) w4 f- g0 {' N# W5 yCompact Flash:
* t( K- E% z9 B5 o9 Z$ t0 ^ - Intermittent failures while accessing Compact Flash card6 [! I% o$ ^( p) N, Q
$ G7 E) @. A: Y; ]! U% B$ N1 H Nios II 5.0 includes a Compact Flash controller peripheral suitable for
" N. E6 n2 g. X+ q interfacing to Compact Flash cards in True IDE mode on Nios development
3 L& p% U4 W- L: {6 s: S2 o3 \ boards. In order for True IDE mode to operate, Compact Flash cards require ! x0 ?6 B/ l2 L. n1 |8 u! \3 s/ @
that the "ATASEL_N" input be driven to ground during power-up.
" G) i* Y/ G7 B0 O! J5 d. q* y; I The Compact Flash controller peripheral includes a configurable power # |( J( G3 y$ Z* v4 s
register used to power-cycle Compact Flash cards in Nios II software - P( X; P7 w. L" D+ M$ B" y6 ^
through a MOSFET on the Nios development boards. However, in certain . ~. N3 v, V$ [8 a' e; n9 T
development boards, power to the Compact Flash card will not be turned ' p' i2 X! b" q% o" m
off completely during this power-cycle operation. Because of this, the . b6 U) d$ L$ P2 n
"ATASEL_N" pin may not be sampled during the power-cycle operation after / m3 n: w! O6 H; ]9 T! y
FPGA configuration when this pin is driven to ground. Instead, "ATASEL_N"
$ [% y" ?# C$ H% r% b6 X% W \ may be sampled by the Compact Flash card when power is first applied to
3 p) |8 ?- g2 Z7 ~4 L the development board, when I/O are not yet driven by the FPGA (before V- q# _/ r: y+ ?4 Y6 B
FPGA configuration).1 I& S4 \: D! u$ K; U# v* D% v0 y
Workaround: If you encounter errors with Compact Flash when using the ! N5 k$ q7 V' V
Nios development boards, please try one of the following workarounds:
5 \9 z+ {( J; `+ P$ A/ f * Try a different Compact Flash card -- Certain cards are more 7 b$ J6 x" |9 c6 c1 }
susceptible to the power-cycling issue than others.
; ?$ @& x9 B2 q! p) `+ ~! V+ | * Modify the Nios development board -- This is recommended for
! H2 H( C' |6 u, ~0 Y7 B users who are familiar and comfortable with board-level
4 b* _: l0 ]$ V& P5 m* b/ M6 R+ Y modifications. Disconnect pin 9 (ATASEL_N) on the Compact Flash
: N# y# h8 m8 [; H5 z socket on your Nios Development Board and tie this pin to ground.
" n+ o( w) D/ ? Note that the Compact Flash socket uses a staggered numbering on
8 w' d, d3 R: V" q2 I the pins (starting from pin 1: 1, 26, 2, 27, ...); please refer
0 G* _5 M1 ]+ s ~. h, ] to the Compact Flash Association specification for right-angle 5 l% w6 {' w* N4 h k: o
surface-mount connectors for exact specifications on this connector.
3 k2 R: M! w: m Caution: This will permanently enable True-IDE mode operation.5 e, ]2 Y$ B1 w2 F( h% j
- Compact Flash card and LCD screen do not work concurrently
" @2 P* T0 [5 A- j3 k8 O: A6 ] If there is a Compact Flash card inserted in the development board, the
# u, X( c" v5 N5 X LCD and other devices connected to the PROTO1 header might not work.
+ l6 g: \) A g; ~' @4 L3 ^ Workaround: Remove the Compact Flash card to ensure proper operation of 7 X- s! {* ?' _' ]& K/ [1 R
the PROTO1 header, or vice versa.
1 g" m3 m0 B7 ~5 c/ E4 p8 G1 b/ K+ v1 s' f
/ a! k- d( O0 i1 W: j F" b在网上找到一个相当不错的CF控制器有兴趣可以研究一下 |
|