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Readme - Compact flash monitor/debug demonstration
1 \& `9 w/ O; P9 L' [9 }GENERAL DESCRIPTION:2 E% k' `1 q& s, G/ t
This distribution contains hardware and software examples suitable for4 H V" }/ p# G
operation of the the Compact Flash interface (True IDE mode) peripheral
: }4 R" K* p0 |6 q7 V; M @: [included in the Nios II 5.0 development kit. This peripheral's register
# _2 R. U- P3 Qmap is equivalent to the compact flash interface previously posted to the 6 j+ g. T* o; ?
www.niosforum.com "Tested IP" area by Microtronix. + S* K) ?& Z |' C
HARDWARE EXAMPLE DESIGNS
! u. \) Q3 ~* u: Z6 {' v; GIncluded with this distribution are several hardware example designs 9 D' }, S! W) ~: x$ U# Z+ x
illustrating how to connect Compact Flash pins to the I/O exported from
) k x8 m$ R6 L; V! \9 J$ m5 Vthe peripheral. The examples supplied are pre-built and tested on the6 o. \8 \* p% D/ q
following development boards:/ k8 M2 b) P; A2 V1 N2 M( ?! R& f
- Nios Development Board, Cyclone Edition (EP1C20)
- b5 Y; n, N- L- F* R% a3 O ~ - Nios Development Board, Cyclone II Edition (EP2C35)7 _/ a# Q* J& K3 \
- Nios Development Board, Stratix Edition (EP1S40)* \8 ?/ O2 _9 V) v( [( O$ i
- Nios Development Board, Stratix II ES Edition (EP2S60ES)- F5 U* i H. |) Q0 A2 @9 M8 Y
+ X1 U! G0 k1 g" b: |( KFor users of the Nios Development Board, Stratix Edition (EP1S10 or EP1S10ES
2 \+ g0 _2 M3 v, i& yAltera devices), it is suggested that you start with the EP1S40 example design
0 i6 E! S J( f% i4 Xand change SOPC Builder board component & Quartus device assignment, and then
7 P& B3 r4 D& w! m" p& ?7 @( {7 E8 bre-compile the design. Do not remove I/O assignments; the I/O assignments for
2 B* N! [. o7 Z: \these three development boards are identical.
. L$ U% u* l. iIn addition, the the Quartus project setting (.qsf) files included with each of" r/ o8 O" D9 o* z9 A3 F
the above hardware examples includes pin-assignments for Compact Flash that you
$ `1 ]4 v, U ymay easily copy to your own custom design that uses Compact Flash.
& @ V& w' W6 E2 j9 w! m( |# Q8 N4 eNote: Hardware example designs in Nios II 5.0 included these same pin
. ^7 o& {0 ~4 O( {2 T1 ~assignments in each design.5 x4 ?( @, P0 l/ W
SOFTWARE EXAMPLES" H* F$ x8 M% J# M5 }" t, s, b
The software included in this package allows rudimentary IDE access to
& D/ h& c9 z* ICompact Flash, including debug routines, hot-swap capability, and
" j7 H5 S* U8 dthe ability to read/write compact flash in either LBA or CHS addressing
* u: `5 j* \" O+ I4 t; B* Amodes. No file system support is provided, though this example would
9 u" ~- g, C% X7 D5 l$ Cserve as a fine starting-point for a higher-level file-system interface.
* @5 k0 J1 U! o8 _) oAdditional software support for the Compact Flash interface is included5 N) v. H3 i( q; _( l1 m r
in the eCOS release for Nios II 5.0, and Micrium MicroC/FS file system,( T, b8 F' M% C8 O& w% L* j
both of which have been tested with the Compact Flash interface ' S- N# k( _. @$ ^
peripheral. These software interfaces do NOT require the software included6 R- W$ w7 Z" O6 p9 d! |6 x' U, y
with distribution, but may be used with the hardware example designs
; X0 o6 ]8 q, _& m9 Lincluded with this distribution.
% g1 I0 u, x% [% KTo build the software example design, open the Nios II IDE, create a new Nios ! i6 Q+ o4 r: v6 K$ i, l; E0 k
II C/C++ application (it is suggested that you start with a template such as
+ p" u/ d7 h$ M8 L"Hello World" or "Blank Project"), then, copy the source-files to the newly
9 B* @9 H* F8 c r! n! @2 ecreated project directory and "refresh" the project contents in the IDE (F5).2 O0 l$ r4 `5 y
Following this, you may build the application. The main() routine is located" E7 g$ y2 h) X, w! k+ I
in file cf_test.c& [1 T* V( r. ^
Note: If you start with hello world, be sure to remove hello_world.c to prevent5 X- J* e2 S& i5 B
conflicts during compilation.
' P u4 F$ K+ n& q3 Q) AREQUIREMENTS:7 A8 \: a0 E+ m" ]
The example software requires an altera_avalon_cf peripheral named "cf"
+ h3 l3 `- {& y5 r- oinstantiated in your SOPC Builder design. In addition, the default LCD y3 h3 d' t! h1 k8 y. l. m" s
interface that is included in "standard" and "full_featured" Nios II example 3 c2 G& i* Z; ]7 ?; {6 r
designs may not be used, as it shares pins with the compact flash socket. & z) g4 m+ F. D2 b
The hardware example designs included with this distribution conform to the
V* y: `$ h1 ?9 ~ Z% aabove requirements.
1 G) _' ~) q( S& C5 o+ lKNOWN ISSUES & WORKAROUNDS:7 b5 E" _$ N3 x
Every effort has been made to make both the Compact Flash interface peripheral2 `! M1 s" E! N' H+ g* \
and software examples perform without flaws. However, certain known issues
- ], |' y3 M$ ?$ P+ |+ e; | fmay prevent Compact Flash card access. 3 n6 V9 x% [+ S7 V/ r5 V
The following are relevant excerpts from the Nios II 5.0 errata discussing ; I" f. h( W, n4 r4 o
Compact Flash:
+ A4 g# J# P5 } - Intermittent failures while accessing Compact Flash card
3 n( F( k6 h. I, ] r6 K9 P; N
# @3 M7 d: r7 I& X5 y Nios II 5.0 includes a Compact Flash controller peripheral suitable for
& ?# e8 j) f3 F) _9 Z0 i interfacing to Compact Flash cards in True IDE mode on Nios development 1 U1 F6 n: v1 T& ~
boards. In order for True IDE mode to operate, Compact Flash cards require ( \8 F2 o# e' \9 ^* |. a/ y
that the "ATASEL_N" input be driven to ground during power-up.7 z$ R$ K0 b m9 S8 @
The Compact Flash controller peripheral includes a configurable power
0 A" S: n6 ]- _. V$ w% J register used to power-cycle Compact Flash cards in Nios II software
" ?' k$ `! ]9 a through a MOSFET on the Nios development boards. However, in certain
* o- G7 f8 A$ I2 U. _8 N6 ~+ F1 ] development boards, power to the Compact Flash card will not be turned " s- ?, G5 s9 M) ~" y
off completely during this power-cycle operation. Because of this, the
3 D r0 X4 W9 ?! K E8 s6 [ "ATASEL_N" pin may not be sampLED during the power-cycle operation after
* j& F9 ?6 R1 z# v FPGA configuration when this pin is driven to ground. Instead, "ATASEL_N"
7 R! O- J# t2 B7 K may be sampled by the Compact Flash card when power is first applied to - v9 \ q5 H- F. I" d+ q
the development board, when I/O are not yet driven by the FPGA (before ' }) ~: E( @( E* [
FPGA configuration).
+ W2 Z1 k; ]: Q, P' @5 R Workaround: If you encounter errors with Compact Flash when using the 3 b& b9 R: @" A0 ?0 J
Nios development boards, please try one of the following workarounds:% u8 h% _' s* D
* Try a different Compact Flash card -- Certain cards are more
& u: f1 b! _+ u; Q4 s) G susceptible to the power-cycling issue than others.
% M# l0 _ G# F: x * Modify the Nios development board -- This is recommended for : }( @* g/ V6 [4 R
users who are familiar and comfortable with board-level
: ~2 [5 G. T: ?0 R- w modifications. Disconnect pin 9 (ATASEL_N) on the Compact Flash 1 M5 ?) g. H8 p5 a7 x! w
socket on your Nios Development Board and tie this pin to ground. & P* ]8 l+ P7 L% Z. F
Note that the Compact Flash socket uses a staggered numbering on ( j# l# j! z R9 ]' C7 d# q
the pins (starting from pin 1: 1, 26, 2, 27, ...); please refer # d! Z/ G6 _) L2 K: _* ~+ H+ w
to the Compact Flash Association specification for right-angle : C3 c7 i# V# f8 s& I
surface-mount connectors for exact specifications on this connector. + n j2 e {. j( X
Caution: This will permanently enable True-IDE mode operation.1 J! i$ q6 t1 t& o( ~! A
- Compact Flash card and LCD screen do not work concurrently7 X$ N# r8 f5 L" K6 n
If there is a Compact Flash card inserted in the development board, the
3 M" _+ Y$ [% B' i* B: G LCD and other devices connected to the PROTO1 header might not work.0 q* E; T( B2 i, A% n
Workaround: Remove the Compact Flash card to ensure proper operation of 3 \) n$ ~4 G Q5 }: h0 X# r
the PROTO1 header, or vice versa.1 [) X4 z2 k4 a" }; Y7 J0 f; t
. b8 C/ q# C; I$ R: Q$ O3 N: g
% ^5 g7 n# K+ {
在网上找到一个相当不错的CF控制器有兴趣可以研究一下 |
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