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Readme - Compact flash monitor/debug demonstration
1 J6 M. d% r( l+ @% y- m9 ]GENERAL DESCRIPTION:! x; ?4 Q" ]( c% G
This distribution contains hardware and software examples suitable for# p3 ]* q# t9 C1 b& _5 m' ~
operation of the the Compact Flash interface (True IDE mode) peripheral
% B& Y u. T1 D' Vincluded in the Nios II 5.0 development kit. This peripheral's register : z5 S- P4 d, I, `6 ^& d( a: V
map is equivalent to the compact flash interface previously posted to the
* R8 }" h. d; q+ B; Twww.niosforum.com "Tested IP" area by Microtronix. 8 O/ E7 [* n) S" ]; E+ z2 | ?5 w
HARDWARE EXAMPLE DESIGNS ' _, T9 u: B; C$ T3 z
Included with this distribution are several hardware example designs 9 r6 t( l1 `5 ]' ~
illustrating how to connect Compact Flash pins to the I/O exported from( F& p8 a# ?& @( R6 {
the peripheral. The examples supplied are pre-built and tested on the* s9 d( i% d9 G/ W) a0 c
following development boards:
) D3 v/ H5 R0 o0 ]: D9 l( d; W& e - Nios Development Board, Cyclone Edition (EP1C20)2 Q0 h- ~, l6 I; [/ k6 j4 r* L: l
- Nios Development Board, Cyclone II Edition (EP2C35). ~: z. N& [- k9 Y6 B) c q
- Nios Development Board, Stratix Edition (EP1S40)
' W+ H( i- T3 y - Nios Development Board, Stratix II ES Edition (EP2S60ES)! t7 X: o" w4 _9 m9 `/ K$ Z8 K
# c: d& t* r8 Z/ \' z5 c$ M$ kFor users of the Nios Development Board, Stratix Edition (EP1S10 or EP1S10ES% ^) D* K) R- T6 l$ N
Altera devices), it is suggested that you start with the EP1S40 example design
8 ` u: X4 M( h3 u- K3 y/ Q. Uand change SOPC Builder board component & Quartus device assignment, and then @0 L) ^; H2 A6 v
re-compile the design. Do not remove I/O assignments; the I/O assignments for
* f: e7 @9 ?1 Rthese three development boards are identical.
7 H% z w3 l8 ~" ^4 {: y' g( _In addition, the the Quartus project setting (.qsf) files included with each of& _, U( p D0 D) g" D* U" V( v- W
the above hardware examples includes pin-assignments for Compact Flash that you - Z* h) c& |5 f/ K8 O9 k9 R o
may easily copy to your own custom design that uses Compact Flash.
! \3 |' m9 W+ E8 t. U, F" \# VNote: Hardware example designs in Nios II 5.0 included these same pin
0 b5 ?4 @5 U+ J7 H* \assignments in each design.
: U) ^4 t" l2 _3 ^3 V$ Z- ^+ f6 CSOFTWARE EXAMPLES! N0 Z6 Q/ S% ^ Y( A$ V9 g
The software included in this package allows rudimentary IDE access to
* O* L, k" X& K5 @' h$ `$ VCompact Flash, including debug routines, hot-swap capability, and " O f$ @! m: Y3 }. x. f+ x. K
the ability to read/write compact flash in either LBA or CHS addressing
" Y2 g1 C# L! T- K* D/ tmodes. No file system support is provided, though this example would
& Q% m- H5 m) Q/ U) N0 B9 z9 Iserve as a fine starting-point for a higher-level file-system interface.
* F; f: J y! p" ?Additional software support for the Compact Flash interface is included; ~! o% h6 c! g4 f3 w. {. U
in the eCOS release for Nios II 5.0, and Micrium MicroC/FS file system," }8 F( M, R- T* t4 O& S
both of which have been tested with the Compact Flash interface : A, J; `- E' U3 {# a3 m: L# [
peripheral. These software interfaces do NOT require the software included8 ^* e i- _, a4 H" f2 G
with distribution, but may be used with the hardware example designs
( \3 k; y8 w+ K$ u5 U& s( F% jincluded with this distribution.
4 q9 r% [; M# P" U% STo build the software example design, open the Nios II IDE, create a new Nios # E* M% e& \; f+ u
II C/C++ application (it is suggested that you start with a template such as
8 L9 e+ N' J# V/ K) ?; V"Hello World" or "Blank Project"), then, copy the source-files to the newly ! h. P; n! }* c
created project directory and "refresh" the project contents in the IDE (F5).7 l' ^1 `2 m' Y5 V0 o' T, t6 l
Following this, you may build the application. The main() routine is located# N2 C7 A8 }, s9 p1 X' h- J
in file cf_test.c0 D @7 F" Q5 ?
Note: If you start with hello world, be sure to remove hello_world.c to prevent
# @* \! @: W) W9 a$ a u( ^3 C' ? hconflicts during compilation.
, B- F! B( l/ _# R7 f8 yREQUIREMENTS:) a, g. ^; a3 j
The example software requires an altera_avalon_cf peripheral named "cf" 0 z4 H; b6 f( }, o6 q% B
instantiated in your SOPC Builder design. In addition, the default LCD [5 b( y! ]7 S1 w9 H1 J* Z* R1 X" s& d* r7 X
interface that is included in "standard" and "full_featured" Nios II example
8 O9 D1 {: k: ^5 W! ydesigns may not be used, as it shares pins with the compact flash socket. ; D3 o9 X# j2 h1 ~% A
The hardware example designs included with this distribution conform to the
% J) Y' I1 _& Z8 qabove requirements.
' T/ t: t! @7 I, g f) H2 [KNOWN ISSUES & WORKAROUNDS:2 d6 h1 e4 ]* ]7 s- ^6 j
Every effort has been made to make both the Compact Flash interface peripheral R0 r# @, g! r5 |" b* D b; o9 n& o
and software examples perform without flaws. However, certain known issues- m* O1 x# S! l$ q1 Z$ t
may prevent Compact Flash card access. - G$ E) W( y+ l* E
The following are relevant excerpts from the Nios II 5.0 errata discussing 9 a8 H' c3 P2 T% M8 K
Compact Flash:
$ r' w' h0 Y+ U3 s: v9 n - Intermittent failures while accessing Compact Flash card
2 [2 j' f- r6 E( n) o3 {8 v
8 P* N/ l6 c2 O: v1 O Nios II 5.0 includes a Compact Flash controller peripheral suitable for
, ?" ?0 r4 c4 d; C" L interfacing to Compact Flash cards in True IDE mode on Nios development
8 B- G! B/ e: a boards. In order for True IDE mode to operate, Compact Flash cards require
3 {" U3 A* I6 o( n/ M that the "ATASEL_N" input be driven to ground during power-up.
# k0 N% j1 @+ b( [: f: U The Compact Flash controller peripheral includes a configurable power
6 z3 X, O' Z, {/ ]' g/ N register used to power-cycle Compact Flash cards in Nios II software 2 O7 `( X. ?$ z" j: [
through a MOSFET on the Nios development boards. However, in certain
; G: |/ \- k3 j- M: F, `+ C development boards, power to the Compact Flash card will not be turned
7 g& u0 U8 _3 O7 i, J5 y+ }: P+ G# R off completely during this power-cycle operation. Because of this, the 4 q+ T$ u: `/ L0 E/ x
"ATASEL_N" pin may not be sampled during the power-cycle operation after
, c1 I/ `8 K6 u% C0 \: Y8 y FPGA configuration when this pin is driven to ground. Instead, "ATASEL_N"
/ i0 d+ A$ x( s8 M+ J4 D may be sampled by the Compact Flash card when power is first applied to
4 Q7 E# V( j) s' B( h the development board, when I/O are not yet driven by the FPGA (before & a, D( s8 p. R' u9 ~4 ^
FPGA configuration)./ Q/ m" N5 J) M6 c/ m
Workaround: If you encounter errors with Compact Flash when using the
, R% e g# Q. r: j! t Nios development boards, please try one of the following workarounds:
- G3 W- c) a$ F+ P S * Try a different Compact Flash card -- Certain cards are more
0 P# T) f" l. O/ d1 [ susceptible to the power-cycling issue than others.6 ]0 J3 ] x4 I
* Modify the Nios development board -- This is recommended for 3 M1 r" B, u$ V. H8 K6 @" Q7 C3 a
users who are familiar and comfortable with board-level 4 q5 P+ B8 |& x8 t; f' t
modifications. Disconnect pin 9 (ATASEL_N) on the Compact Flash 4 I5 a5 a+ P+ P8 `: ?& @
socket on your Nios Development Board and tie this pin to ground.
$ ]2 y- }3 B- r2 x# U% e, m Note that the Compact Flash socket uses a staggered numbering on
5 W" l% d5 j4 B$ O5 ]) P' p the pins (starting from pin 1: 1, 26, 2, 27, ...); please refer
* B) t* l6 A* e( i3 S9 h( @2 q3 J6 I to the Compact Flash Association specification for right-angle : N8 N1 w$ _* `
surface-mount connectors for exact specifications on this connector. 7 V- s5 W! C3 ~5 w3 d. t0 {6 b
Caution: This will permanently enable True-IDE mode operation.
6 j% b. ?6 h) K# F" j" ` - Compact Flash card and LCD screen do not work concurrently8 o# i7 g# l- H# u* V. @; S% f% X: b
If there is a Compact Flash card inserted in the development board, the 5 Y. M& |& E# R7 Q
LCD and other devices connected to the PROTO1 header might not work., a) p1 w9 V. ^4 e
Workaround: Remove the Compact Flash card to ensure proper operation of ) p1 H& G3 |9 ?0 {. j$ q
the PROTO1 header, or vice versa.& R0 w1 Y7 E1 T1 `5 a7 n
9 {6 @% P v7 [$ O
7 r0 q% Z5 V5 L; {' }
在网上找到一个相当不错的CF控制器有兴趣可以研究一下 |
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