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Readme - Compact flash monitor/debug demonstration' U! S, f5 _: T, S4 M( |( w% @
GENERAL DESCRIPTION:" ~; n+ t, y: B# g7 y
This distribution contains hardware and software examples suitable for
' v; ]( p/ v, a8 S {! C+ voperation of the the Compact Flash interface (True IDE mode) peripheral
" S2 Q/ P* m) O* k% _3 O+ p0 Qincluded in the Nios II 5.0 development kit. This peripheral's register
# z E0 D# _; B* l( u5 L9 @map is equivalent to the compact flash interface previously posted to the
1 C+ K% b; L Q4 q# S+ |www.niosforum.com "Tested IP" area by Microtronix. ) d: X$ e) X! M8 r
HARDWARE EXAMPLE DESIGNS , e) b( q8 u+ U- }! V$ I8 }% F
Included with this distribution are several hardware example designs ! B, Q* `! M# U- S: k
illustrating how to connect Compact Flash pins to the I/O exported from0 q" o$ S3 h. e
the peripheral. The examples supplied are pre-built and tested on the, N$ R7 h/ o- N
following development boards:
8 r4 }% V1 O2 x/ z8 ]* N - Nios Development Board, Cyclone Edition (EP1C20)
1 G! e/ @$ m8 g3 `9 Z, h - Nios Development Board, Cyclone II Edition (EP2C35)) c0 [" ~% T1 j$ W$ M
- Nios Development Board, Stratix Edition (EP1S40). Q) C8 \7 I& k I
- Nios Development Board, Stratix II ES Edition (EP2S60ES)
3 ?+ u, r6 H: U+ L9 O2 a" | : }2 o. Z' p% P9 Q. Y
For users of the Nios Development Board, Stratix Edition (EP1S10 or EP1S10ES
, |; j/ T. R ^9 h7 rAltera devices), it is suggested that you start with the EP1S40 example design1 m8 A9 f( }! I0 |3 Y9 `
and change SOPC Builder board component & Quartus device assignment, and then
% y3 j9 d% G) F& z) g. n. ere-compile the design. Do not remove I/O assignments; the I/O assignments for
4 ?8 O7 u0 U2 q6 r1 Z' X, S% Uthese three development boards are identical.
# U7 k% H& e% r b: [In addition, the the Quartus project setting (.qsf) files included with each of
6 V: b' h+ Y' @3 ?the above hardware examples includes pin-assignments for Compact Flash that you P2 ?0 f" i! z1 C# Y
may easily copy to your own custom design that uses Compact Flash.! j, c9 Q! n, T0 K6 u
Note: Hardware example designs in Nios II 5.0 included these same pin
. f' O0 v2 y% @& l; xassignments in each design.
" w; M4 ?5 E3 U7 [& p7 }+ Y; tSOFTWARE EXAMPLES9 O6 E. U9 h0 {/ o* N$ \
The software included in this package allows rudimentary IDE access to1 a1 h8 Q; L& a, R t
Compact Flash, including debug routines, hot-swap capability, and
6 f, X/ C# k+ J1 T% X: Qthe ability to read/write compact flash in either LBA or CHS addressing- |& e4 @- u# n2 _8 U
modes. No file system support is provided, though this example would
, t; Q/ c5 G/ \* F" `serve as a fine starting-point for a higher-level file-system interface.
8 O' v# c+ G! N% y9 {Additional software support for the Compact Flash interface is included# x% `, C2 f% _
in the eCOS release for Nios II 5.0, and Micrium MicroC/FS file system,1 _+ H6 ^2 W! X3 f W p( p/ [
both of which have been tested with the Compact Flash interface ; g: X6 m; |7 Z7 A! _% i( ^
peripheral. These software interfaces do NOT require the software included8 L/ }2 G) U4 K- r. A6 A- [
with distribution, but may be used with the hardware example designs- T1 |. \& Y: G
included with this distribution.
: _3 `3 d: O# g; `# g4 M- iTo build the software example design, open the Nios II IDE, create a new Nios : Q w* N, m4 ~+ }+ q
II C/C++ application (it is suggested that you start with a template such as / l% t9 s0 D3 _* ]! Q6 R# A
"Hello World" or "Blank Project"), then, copy the source-files to the newly
& c" I9 _. D( G# `2 m9 [9 lcreated project directory and "refresh" the project contents in the IDE (F5).
/ _! g2 i* N: q) h0 Z9 Z) yFollowing this, you may build the application. The main() routine is located$ M# N: E# o V) D% l' ~
in file cf_test.c
5 }* J& q0 P" l1 i8 \+ S( i( `1 P" BNote: If you start with hello world, be sure to remove hello_world.c to prevent
, \- o3 Q6 Q2 p* A% e L* m, Pconflicts during compilation.
9 S6 G# u/ f4 G& j1 oREQUIREMENTS:
9 D u( d1 y B% eThe example software requires an altera_avalon_cf peripheral named "cf"
( Y7 T6 X+ A, S( ~0 q* @instantiated in your SOPC Builder design. In addition, the default LCD - l5 [5 U; L9 [& r7 t4 {
interface that is included in "standard" and "full_featured" Nios II example
5 u0 V4 z k" J g% y0 V- }6 j O( D& rdesigns may not be used, as it shares pins with the compact flash socket.
0 f% G, H. C, q# H5 R. U0 h! HThe hardware example designs included with this distribution conform to the
! s/ _0 Q1 A4 M& `+ h8 {above requirements.. D2 Z( D9 ^9 r q2 J# Z0 l5 v
KNOWN ISSUES & WORKAROUNDS:
3 Q" L0 ?8 l* T/ c8 h1 ^Every effort has been made to make both the Compact Flash interface peripheral
5 m3 w8 E/ `& Aand software examples perform without flaws. However, certain known issues
5 k* X6 `; ~, }7 ^may prevent Compact Flash card access.
# ^# W* [ e+ m4 ?& N; c2 r" vThe following are relevant excerpts from the Nios II 5.0 errata discussing
o: ~5 |) r& T# e# b( @Compact Flash:: ^% @) I6 J0 M0 s: p
- Intermittent failures while accessing Compact Flash card
- I4 ]: y) @) z E2 D# ?( f
9 E% \# C; F# j9 W z Nios II 5.0 includes a Compact Flash controller peripheral suitable for
/ Y S( e- R/ X [% n interfacing to Compact Flash cards in True IDE mode on Nios development / k7 S7 r) R$ F. f6 r/ \
boards. In order for True IDE mode to operate, Compact Flash cards require h- }! \/ r4 E, T5 @6 h' V6 s
that the "ATASEL_N" input be driven to ground during power-up.+ @5 C9 ^, F( A: b$ E
The Compact Flash controller peripheral includes a configurable power 7 Q1 w% `% _2 i+ l
register used to power-cycle Compact Flash cards in Nios II software
7 ]$ u1 P" O: ?& k through a MOSFET on the Nios development boards. However, in certain 6 h- t q) y3 i) F$ p0 m [
development boards, power to the Compact Flash card will not be turned % }7 g! x2 B2 |
off completely during this power-cycle operation. Because of this, the ; T+ C1 x+ P6 W5 P
"ATASEL_N" pin may not be sampled during the power-cycle operation after 9 ]0 I/ |* }% x
FPGA configuration when this pin is driven to ground. Instead, "ATASEL_N"
$ a* ?. M- {! n$ e" k may be sampled by the Compact Flash card when power is first applied to
- \4 Y3 [8 A' a2 H; _1 k/ G the development board, when I/O are not yet driven by the FPGA (before
1 h, u4 L: w% [- j- z* K, u! c+ K FPGA configuration).# l6 [; h$ ` `" M6 f) D
Workaround: If you encounter errors with Compact Flash when using the
& \* i4 h9 a, e" t; Z Nios development boards, please try one of the following workarounds:( x& b9 y: e: Z" ?: k1 I
* Try a different Compact Flash card -- Certain cards are more
; J9 P8 f3 u3 E$ N1 b% m* ?8 V susceptible to the power-cycling issue than others.
/ }6 _2 _! c7 l. J8 [ * Modify the Nios development board -- This is recommended for 4 z5 K1 l7 L8 J: j4 f
users who are familiar and comfortable with board-level # _4 g4 f/ Y0 f& o1 V4 M% R
modifications. Disconnect pin 9 (ATASEL_N) on the Compact Flash 5 P: V# ?* w$ w$ p
socket on your Nios Development Board and tie this pin to ground.
5 ~% Z+ |1 j9 T" f& a8 n Note that the Compact Flash socket uses a staggered numbering on 9 N ^- Q1 e, B- C, Q! c
the pins (starting from pin 1: 1, 26, 2, 27, ...); please refer
! d. y) B8 ~+ o' c" q$ z/ [: s to the Compact Flash Association specification for right-angle 9 r6 L- E6 I: ^6 Q6 z( I
surface-mount connectors for exact specifications on this connector. 8 h# }( S# |5 H2 k7 s% ]" c
Caution: This will permanently enable True-IDE mode operation.
. Y& h M- j. i, s1 _5 A J' L- M - Compact Flash card and LCD screen do not work concurrently
N2 B! o! T Q: I# ?' w If there is a Compact Flash card inserted in the development board, the " D# S# e% v+ p5 d, d
LCD and other devices connected to the PROTO1 header might not work.$ k0 f" O2 M3 U f
Workaround: Remove the Compact Flash card to ensure proper operation of 3 |; j( O$ Z4 W: V: P6 X
the PROTO1 header, or vice versa.& g" G" C/ q* \* M& G
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$ [8 D% }9 m: Z4 z! [- N
在网上找到一个相当不错的CF控制器有兴趣可以研究一下 |
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