版主
主题
帖子
积分10609
阅读权限200
注册时间2008-11-22
最后登录1970-1-1
在线时间 小时
|
////////////////////////////////////////////////////////////////////3 b; R7 @! Y, d/ m( V- @5 a
// FileName: "Fifo.v"
; `8 s2 f7 Q* n! L) f% I// Author : Venkata Ramana Kalapatapu. O5 z: T& s& j3 k* ^
// Company : Sand Microelectronics Inc.2 w! `+ I Q5 {# X4 U7 w. j$ `
// (now a part of Synopsys, Inc.),% v" N6 }" E* C" L/ m
// Profile : Sand develops Simulation Models, Synthesizable Cores and
- V$ T. c+ T' D) h4 y+ k// Performance Analysis Tools for Processors, buses and
1 ^# q2 I6 g1 _4 S. {5 N// memory products. Sand's products include models for
9 Q% s+ C5 g0 E1 f1 L// industry-standard components and custom-developed models/ y" l) E4 F: C2 c
// for specific simulation environments.
& q& ^2 o7 l4 u# a+ t" t% W3 M//
3 @* I- f9 {) p. H" |////////////////////////////////////////////////////////////////////
5 w; u0 d% o. D; d" k3 z
) h2 H8 F) x& V; z( w: ]- r$ u`define FWIDTH 32 // Width of the FIFO.8 V+ M$ W( y u1 V* T
`define FDEPTH 4 // Depth of the FIFO.
1 ?2 z: J2 c. E" A$ N0 ~`define FCWIDTH 2 // Counter Width of the FIFO 2 to power
. I% x, F) I; I. o // FCWIDTH = FDEPTH.+ {5 E+ ^3 m B5 I0 o
module fifo( Clk,
9 m8 [; W4 r& a: M& j! y RstN,( w" {+ O) j4 m7 M o/ a
Data_In,; z# Q+ v% u3 p6 P4 b
FClrN,
5 I) d) O" D% j: o6 t FInN,# B& A7 J ?# c) D$ S, U/ j2 J w
FOutN,
1 o( b. c2 `. }2 {- ~8 @ F_Data,, w% k2 I1 n/ v ]& K0 j
F_FullN,( m; t& R$ G2 f; k, U, \, h4 ^& n6 U
F_LastN,$ l) z; k( D8 b# E
F_SLastN,% H- J# j3 H2 \* r
F_FirstN,
0 Q2 G, `. D& E) x* k- l F_EmptyN
% g1 a) |! |! {6 i8 | );
* }9 i+ k- m4 a: L
7 x6 g n( b8 u& R n8 r8 A5 Minput Clk; // CLK signal.. F3 k8 T& \( B) K F) E
input RstN; // Low Asserted Reset signal.
' R( c) w5 E8 o4 c% P( E2 linput [(`FWIDTH-1):0] Data_In; // Data into FIFO.
' M. I. R0 b: J* g5 A3 l9 E5 s0 xinput FInN; // Write into FIFO Signal.0 n& ^7 E$ P5 W7 q- K7 y- Y
input FClrN; // Clear signal to FIFO.
& I7 J! Q. u9 L7 b- ~: K" Y1 oinput FOutN; // Read from FIFO signal.
& m0 N. M5 K" Q2 F0 F5 Joutput [(`FWIDTH-1):0] F_Data; // FIFO data out.
0 L3 O; f# A3 q, i6 ~output F_FullN; // FIFO full indicating signal.5 B7 c# \3 L' @8 O$ J% @
output F_EmptyN; // FIFO empty indicating signal.
' ^( c) F: @3 t- f. D0 K+ ~- poutput F_LastN; // FIFO Last but one signal.
, \+ h& j M5 Boutput F_SLastN; // FIFO SLast but one signal.# @2 A% b. c9 C7 `+ n
output F_FirstN; // Signal indicating only one
/ e1 ^& `2 t/ V' u! Y // word in FIFO.6 k) G3 t3 N; Q- P* [9 H
8 Y4 }% i4 v$ U+ @: Wreg F_FullN;) O5 K$ j4 ]. r% M
reg F_EmptyN;
; d7 K) M5 c+ ~- Hreg F_LastN;
3 q$ j ~0 T V$ ~( m5 O: }5 k( c. ?reg F_SLastN;: {5 U4 [1 k: D9 _/ l& `
reg F_FirstN;' I" o$ M) v* J+ `6 k4 [5 Q
reg [`FCWIDTH:0] fcounter; //counter indicates num of data in FIFO
5 K4 f; Z2 t X- _ Preg [(`FCWIDTH-1):0] rd_ptr; // Current read pointer.
. x& _+ r% N+ }. U! {' r/ [reg [(`FCWIDTH-1):0] wr_ptr; // Current write pointer.( O. j% [. V5 H! _! E$ ~/ Z
wire [(`FWIDTH-1):0] FIFODataOut; // Data out from FIFO MemBlk
' _3 Q; g; p. ?# ywire [(`FWIDTH-1):0] FIFODataIn; // Data into FIFO MemBlk
5 j8 r; v T( G7 Uwire ReadN = FOutN;
+ X; F0 b7 R8 H, H5 f1 Q) Jwire WriteN = FInN;) f' _4 ~" w0 y6 N" b6 ?5 u
assign F_Data = FIFODataOut;
9 ]0 e7 r" j* F* C" Kassign FIFODataIn = Data_In;( b$ b1 l7 j. M" z
" Y- t n1 v( f8 n4 _7 b$ j
FIFO_MEM_BLK memblk(.clk(Clk),( j. O8 u; K' ^1 o8 o Q. h
.writeN(WriteN),
' [; _# u+ q, K .rd_addr(rd_ptr),/ X! {" m1 e) l" O8 b
.wr_addr(wr_ptr),3 _2 Z/ g" k" z. f9 G
.data_in(FIFODataIn),
6 C% ^3 F$ O( v/ V1 U7 d+ n) E .data_out(FIFODataOut)6 x6 T" S1 A# h7 ?
);8 {, k9 d& V% K9 X- z' F
// Control circuitry for FIFO. If reset or clr signal is asserted,0 A' {3 b; u3 X R/ e
// all the counters are set to 0. If write only the write counter
8 \/ D5 @8 Z+ ?2 Y5 j% R // is incremented else if read only read counter is incremented2 u0 _) L/ z8 J0 V5 K. c
// else if both, read and write counters are incremented.
8 n1 x0 [8 @1 i) N // fcounter indicates the num of items in the FIFO. Write only
& w, C1 T6 L+ }/ O% v, g // increments the fcounter, read only decrements the counter, and0 A( d0 ~: a1 q% g9 H0 |
// read && write doesn't change the counter value./ \: R' F7 P3 O) t7 s+ X9 h( O
always @(posedge Clk or negedge RstN)% E1 l4 i5 n/ X$ h4 j% n
begin2 N* Q( U4 s7 \3 q* k
if(!RstN) begin
, G6 H& S" q" w; X; S, j! @0 m fcounter <= 0; `/ ^7 v/ R6 C$ n- r; _
rd_ptr <= 0;
3 q; Z) K# q/ X wr_ptr <= 0;
' \' v9 ?- [5 c0 f) c) p9 e% A end7 G0 X) d; ?' `* o
else begin- A: ^0 F( p, d( P0 R: W
if(!FClrN ) begin: }8 z( |' I) ^1 L# X# d/ s5 |$ i
fcounter <= 0;
# N" J3 y) y0 w1 ? rd_ptr <= 0;
S q# O' V2 I/ g wr_ptr <= 0;& l+ |) {. |/ }1 c5 a0 o
end
. r0 }0 t6 |# I! v% e else begin- B0 {0 c# m0 f
if(!WriteN && F_FullN)+ Q5 r# ?( z% R8 I9 B4 J, F
wr_ptr <= wr_ptr + 1;
7 U4 n5 ?) S3 m if(!ReadN && F_EmptyN)
K8 [, ?: ]& a9 g- x rd_ptr <= rd_ptr + 1;) z4 o& ~5 e6 m: _, w4 Q
if(!WriteN && ReadN && F_FullN)
( p, g! J& @; M; t* O9 d fcounter <= fcounter + 1;
1 d0 x: i, ^) Y3 E# F; c else if(WriteN && !ReadN && F_EmptyN)
3 O5 E* e5 L+ W( ?8 Y fcounter <= fcounter - 1;
5 r5 c9 t) C' _# G end* k! w+ ?# y! C8 d
end
4 o, N( I1 @, ~ end
( `" n# `$ B' A // All the FIFO status signals depends on the value of fcounter.
, a+ i3 K9 T! }$ c. n/ X- P# |1 q // If the fcounter is equal to fdepth, indicates FIFO is full.
# C5 c& V# ^0 G1 J" E* \ // If the fcounter is equal to zero, indicates the FIFO is empty.0 V( Q9 O6 s3 K
// F_EmptyN signal indicates FIFO Empty Status. By default it is
5 B9 y4 q& d p6 ?3 F // asserted, indicating the FIFO is empty. After the First Data is$ X' s$ n ~" v8 x4 Z0 I+ {
// put into the FIFO the signal is deasserted.
: s! ~- ~' B3 z4 d always @(posedge Clk or negedge RstN): X( ^ S8 x$ y- `# X! c
begin
: b% ^; Q2 G- f3 X7 [ if(!RstN)$ G. ]+ |4 m6 s" }
F_EmptyN <= 1'b0;/ S9 g v1 s, G4 K
else begin) V6 H: T" J, y
if(FClrN==1'b1) begin7 _" U/ M0 c; [- c0 F* g/ I
if(F_EmptyN==1'b0 && WriteN==1'b0)
. Q+ K0 `6 l q' X" D" m: v F_EmptyN <= 1'b1;
[* b: J0 y+ T8 ? else if(F_FirstN==1'b0 && ReadN==1'b0 && WriteN==1'b1)
+ ]6 g$ \( l2 n+ ] F_EmptyN <= 1'b0;+ V L) g8 E4 i$ K% u
end9 M" t) P3 b9 Y8 X0 J
else
6 f2 e' | I5 }2 }- Q F_EmptyN <= 1'b0;- E' x$ v' B" b3 H
end4 V% G) q1 W4 s3 ^# m+ ~
end; H6 |& \8 T. U2 d6 [
// F_FirstN signal indicates that there is only one datum sitting
6 g9 b0 Y& d" `0 |# K+ A // in the FIFO. When the FIFO is empty and a write to FIFO occurs,8 ^; F- ~; D: R9 D% R; b7 Q
// this signal gets asserted.& x& M) j8 r' R& [7 y. i
always @(posedge Clk or negedge RstN)$ Q7 B" P% }0 v% N) u Y) P0 T
begin
* ]% e1 T3 g. E8 y% Y if(!RstN)
* I- \, O4 j- J/ s: V9 t9 j F_FirstN <= 1'b1;
+ |$ M5 G B4 N8 q( \/ J1 } else begin. K! Q. t) k8 X3 F( E7 m% `& d$ F c
if(FClrN==1'b1) begin( w3 a' l. ^: F! `- B
if((F_EmptyN==1'b0 && WriteN==1'b0) ||& j9 t$ B, r- H, [" b6 y
(fcounter==2 && ReadN==1'b0 && WriteN==1'b1))
0 G. V- A( d" y3 u2 k* i- q F_FirstN <= 1'b0;
8 D. }2 d: b9 k/ a8 ~0 n% H else if (F_FirstN==1'b0 && (WriteN ^ ReadN)) d$ z6 v: ]1 M' v( q
F_FirstN <= 1'b1;& `! d4 G4 q# q
end
2 ]1 ?4 |: X- G; T* t X else begin
% p; Z) P$ r' ^5 h1 k F_FirstN <= 1'b1;7 T* `. n- \+ i! z: E' M( | Z
end u# v# d0 g( J
end
& ]( i/ o* d9 z8 w end
2 {% G0 q9 V3 c% s' m! G6 P7 s; n% }' H
// F_SLastN indicates that there is space for only two data words" l; K. R# `, Q% X; M
//in the FIFO.& s. i: k3 j2 \/ l/ S2 e. c" b ?/ y6 r
always @(posedge Clk or negedge RstN)
# H6 k2 t8 T/ u begin
# P1 B B5 F2 f; Z+ O5 v) s if(!RstN)
: ?- w* b) p2 s9 S F_SLastN <= 1'b1; I3 g) p% `1 m- j: S2 F" q# J
else begin
# X! G. F3 L; C# Y( F if(FClrN==1'b1) begin$ R! n! q$ s+ O" p
if( (F_LastN==1'b0 && ReadN==1'b0 && WriteN==1'b1) ||6 e2 z% S8 e7 X) j! A6 N
(fcounter == (`FDEPTH-3) && WriteN==1'b0 && ReadN==1'b1))
3 C. O, M, s) }) E F_SLastN <= 1'b0;; }( O! x, {: W" m; ^4 \8 c4 R
5 ]) l8 \& E& s4 p else if(F_SLastN==1'b0 && (ReadN ^ WriteN) )
) ~1 C8 @! U" s6 w0 B! Z0 n F_SLastN <= 1'b1;
2 o1 Y! q( H* B: `& J end+ [6 {% g$ ]% h/ J7 L/ T8 Q0 {
else
; \ l' u) f+ @& p8 ~6 M( N F_SLastN <= 1'b1;1 D2 g/ ~3 M; [# F q. J( Z$ i
end" _7 v! |3 `4 _7 u! E2 Z% y0 f5 {2 w
end
+ f0 a# ^% |( Q7 N5 k# u( W // F_LastN indicates that there is one space for only one data( @# c( [4 R% ^1 L7 L
// word in the FIFO./ a; E$ p1 e+ w
always @(posedge Clk or negedge RstN)9 l" g7 ~0 a! i, ?, V
begin+ A9 o2 q8 O) n8 c5 h2 S: @8 f
if(!RstN)- q8 O7 K5 ]+ K, U3 y5 r9 ]& O8 S/ Y
F_LastN <= 1'b1;- `% T! D2 f( l: V
else begin
% ] p) \; {+ s* ^- D8 M if(FClrN==1'b1) begin- E% z H$ x8 W6 c* A$ y
if ((F_FullN==1'b0 && ReadN==1'b0) ||- u o9 @ @% i1 y
(fcounter == (`FDEPTH-2) && WriteN==1'b0 && ReadN==1'b1))
7 w7 F$ s, P2 V4 d F_LastN <= 1'b0;
9 V+ S) k0 x2 i: N else if(F_LastN==1'b0 && (ReadN ^ WriteN) )2 ]) A/ @/ a9 U5 E" x8 t1 Z
F_LastN <= 1'b1;
# o) f! l. j' q5 V; c& V* g end
% k% F- T" d+ ~* v. E6 F else( \$ P3 E" p2 m' j3 Y" ]! z: h
F_LastN <= 1'b1;6 d! B- ^7 ]7 v2 | x
end
& f& o- w' @5 y6 _. a# P& s4 C- [ end+ X$ g2 |3 Q3 C# x8 U) W5 F) w: z
' D6 I6 w" A! w C9 L0 t
// F_FullN indicates that the FIFO is full.+ _3 Q7 Z- x3 S8 M3 D' `. Y
always @(posedge Clk or negedge RstN): o [1 q* F6 s; v
begin2 m$ y* ~& K' o4 X* L, }/ r3 d( Y4 l
if(!RstN)
6 e7 J$ y: I4 |6 b6 t% w F_FullN <= 1'b1;
% z N0 M* F4 J! j O else begin
" @/ M$ h# @; d0 f) x$ n/ ?; T if(FClrN==1'b1) begin& T+ v W9 e- o1 S0 ^5 p Y/ T
if (F_LastN==1'b0 && WriteN==1'b0 && ReadN==1'b1)
$ J H- K8 v# x- _ R F_FullN <= 1'b0;
8 P. I, [' N3 G& X else if(F_FullN==1'b0 && ReadN==1'b0)
) o8 e( e) m5 v5 U F_FullN <= 1'b1;
# D F& }( R Z0 `2 R" W8 w end( g. Z& Y3 [# T1 B
else( `* ^! b" m8 J9 A% c) \
F_FullN <= 1'b1;2 G0 B" v3 W1 o+ l7 j
end6 A) B+ S+ m: w8 `$ u5 t5 x
end
% v! b3 l. _" u0 I; n# Lendmodule
N/ {) l5 S$ V8 V" f; u: [! ?7 p) c8 P6 e5 G0 d
' `0 t4 B% u+ u3 O6 l0 }& t
///////////////////////////////////////////////////////////////////5 [$ `* s9 J) a" h$ }4 N4 M
//. G, U- N. \5 k0 v5 D5 A' m( x+ d
//4 j5 S" \7 j% I6 r5 S
// Configurable memory block for fifo. The width of the mem
$ T' o3 {4 Z; Z! h1 d9 }// block is configured via FWIDTH. All the data into fifo is done
/ \0 I5 K3 F4 a// synchronous to block.
b; l p( l' J//
0 V2 V; c! e. O, v! d// Author : Venkata Ramana Kalapatapu
1 W0 S1 J4 ~; n+ @" }: ^) M//6 X8 h7 `, n8 b) p# x3 q. X
///////////////////////////////////////////////////////////////////; `$ x# |$ e& u
module FIFO_MEM_BLK( clk,
4 b7 V, ^ @; R: Z e$ J writeN,6 ~" F0 A7 L1 Q9 c. w' [
wr_addr,
; C' C+ ?# G6 {# u rd_addr,& S! n" o4 Q# K2 z" n
data_in,
: m& U* m1 O5 ? data_out
3 H1 b( r, x' ^# `6 e* ~ );
* d3 p: G6 E' Q# i9 h) @- j7 y3 e& Z x
input clk; // input clk.4 O+ s6 \. N; [' o' a8 D# }' ~, w, j, @
input writeN; // Write Signal to put data into fifo.! o4 _0 Q5 s1 ^1 l; u e
input [(`FCWIDTH-1):0] wr_addr; // Write Address.
9 Q, Y1 A# E) o6 l; ?input [(`FCWIDTH-1):0] rd_addr; // Read Address.% { E0 r7 o$ G7 F! l/ `
input [(`FWIDTH-1):0] data_in; // DataIn in to Memory Block
) d5 C) \9 x! coutput [(`FWIDTH-1):0] data_out; // Data Out from the Memory
% T* F/ u+ [9 P- f // Block(FIFO)7 }/ }8 j; Q7 I* c# g0 v4 q
wire [(`FWIDTH-1):0] data_out;
! J6 ?8 f! V6 r0 y- D5 Q' Vreg [(`FWIDTH-1):0] FIFO[0:(`FDEPTH-1)];
" q6 R5 b* c7 y) N/ b1 _- ~: z nassign data_out = FIFO[rd_addr];# V$ D+ i$ D5 p9 }. D7 @
always @(posedge clk)7 Q# \* j) m* |% S i+ G
begin- Z+ \% R" `3 Z D
if(writeN==1'b0)
5 X3 F. G5 |; T FIFO[wr_addr] <= data_in;
0 n2 D1 ^8 }) L3 w& F, b2 ]) Gend
% C& U$ ^7 j; K, S& u8 }! {endmodule |
|