自己塔建AXI STREAM TFT IP核

kenson · 发表于 2019-10-24 17:54

功能源码

//----------------------------------------------------------------------------
// tft_lcd - module
//----------------------------------------------------------------------------
// IMPORTANT:
// DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
//
// SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
//
// TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
// PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
// OF THE USER_LOGIC ENTITY.
//----------------------------------------------------------------------------
//
// ***************************************************************************
// ** Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.          **
// **                                                                      **
// ** Xilinx, Inc.                                                       **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"       **
// ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND    **
// ** SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,       **
// ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,       **
// ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION          **
// ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,    **
// ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE    **
// ** FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY             **
// ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE             **
// ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR       **
// ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF    **
// ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS    **
// ** FOR A PARTICULAR PURPOSE.                                           **
// **                                                                      **
// ***************************************************************************
//
//----------------------------------------------------------------------------
// Filename:       tft_lcd
// Version:          1.00.a
// Description:    Example Axi Streaming core (Verilog).
// Date:             Thu Oct 24 17:52:44 2019 (by Create and Import Peripheral Wizard)
// Verilog Standard:  Verilog-2001
//----------------------------------------------------------------------------
// Naming Conventions:
// active low signals:                   "*_n"
// clock signals:                      "clk", "clk_div#", "clk_#x"
// reset signals:                      "rst", "rst_n"
// generics:                            "C_*"
// user defined types:                   "*_TYPE"
// state machine next state:             "*_ns"
// state machine current state:          "*_cs"
// combinatorial signals:                "*_com"
// pipelined or register delay signals: "*_d#"
// counter signals:                      "*cnt*"
// clock enable signals:                "*_ce"
// internal version of output port:    "*_i"
// device pins:                         "*_pin"
// ports:                               "- Names begin with Uppercase"
// processes:                            "*_PROCESS"
// component instantiations:             "<ENTITY_>I_<#|FUNC>"
//----------------------------------------------------------------------------

////////////////////////////////////////////////////////////////////////////////
//
//
// Definition of Ports
// ACLK             : Synchronous clock
// ARESETN          : System reset, active low
// S_AXIS_TREADY  : Ready to accept data in
// S_AXIS_TDATA :  Data in
// S_AXIS_TLAST : Optional data in qualifier
// S_AXIS_TVALID  : Data in is valid
// M_AXIS_TVALID  :  Data out is valid
// M_AXIS_TDATA : Data Out
// M_AXIS_TLAST : Optional data out qualifier
// M_AXIS_TREADY  : Connected slave device is ready to accept data out
//
////////////////////////////////////////////////////////////////////////////////

//----------------------------------------
// Module Section
//----------------------------------------
module tft_lcd
(
// ADD USER PORTS BELOW THIS LINE
// -- USER ports added here
// ADD USER PORTS ABOVE THIS LINE

// DO NOT EDIT BELOW THIS LINE ////////////////////
// Bus protocol ports, do not add or delete.
ACLK,
ARESETN,
S_AXIS_TREADY,
S_AXIS_TDATA,
S_AXIS_TLAST,
S_AXIS_TVALID,
M_AXIS_TVALID,
M_AXIS_TDATA,
M_AXIS_TLAST,
M_AXIS_TREADY
// DO NOT EDIT ABOVE THIS LINE ////////////////////
);

// ADD USER PORTS BELOW THIS LINE
// -- USER ports added here
// ADD USER PORTS ABOVE THIS LINE

input                                  ACLK;
input                                  ARESETN;
output                                  S_AXIS_TREADY;
input    [31 : 0]                      S_AXIS_TDATA;
input                                  S_AXIS_TLAST;
input                                  S_AXIS_TVALID;
output                                  M_AXIS_TVALID;
output    [31 : 0]                      M_AXIS_TDATA;
output                                  M_AXIS_TLAST;
input                                  M_AXIS_TREADY;

// ADD USER PARAMETERS BELOW THIS LINE
// --USER parameters added here
// ADD USER PARAMETERS ABOVE THIS LINE

//----------------------------------------
// Implementation Section
//----------------------------------------
// In this section, we povide an example implementation of MODULE tft_lcd
// that does the following:
//
// 1. Read all inputs
// 2. Add each input to the contents of register 'sum' which
// acts as an accumulator
// 3. After all the inputs have been read, write out the
// content of 'sum' into the output stream NUMBER_OF_OUTPUT_WORDS times
//
// You will need to modify this example for
// MODULE tft_lcd to implement your coprocessor

// Total number of input data.
localparam NUMBER_OF_INPUT_WORDS  = 8;

// Total number of output data
localparam NUMBER_OF_OUTPUT_WORDS = 8;

// Define the states of state machine
localparam Idle  = 3'b100;
localparam Read_Inputs = 3'b010;
localparam Write_Outputs  = 3'b001;

reg [2:0] state;

// Accumulator to hold sum of inputs read at any point in time
reg [31:0] sum;

// Counters to store the number inputs read & outputs written
reg [NUMBER_OF_INPUT_WORDS - 1:0] nr_of_reads;
reg [NUMBER_OF_OUTPUT_WORDS - 1:0] nr_of_writes;

// CAUTION:
// The sequence in which data are read in should be
// consistent with the sequence they are written in the
// driver's tft_lcd.c file

assign S_AXIS_TREADY  = (state == Read_Inputs);
assign M_AXIS_TVALID = (state == Write_Outputs);

assign M_AXIS_TDATA = sum;
assign M_AXIS_TLAST = 1'b0;

always @(posedge ACLK)
begin  // process The_SW_accelerator
   if (!ARESETN)             // Synchronous reset (active low)
      begin
         // CAUTION: make sure your reset polarity is consistent with the
         // system reset polarity
         state       <= Idle;
         nr_of_reads  <= 0;
         nr_of_writes <= 0;
         sum       <= 0;
      end
   else
      case (state)
      Idle:
         if (S_AXIS_TVALID == 1)
         begin
            state    <= Read_Inputs;
            nr_of_reads <= NUMBER_OF_INPUT_WORDS - 1;
            sum       <= 0;
         end

      Read_Inputs:
         if (S_AXIS_TVALID == 1)
         begin
            // Coprocessor function (Adding) happens here
            sum       <= sum + S_AXIS_TDATA;
            if (nr_of_reads == 0)
            begin
               state       <= Write_Outputs;
               nr_of_writes <= NUMBER_OF_OUTPUT_WORDS - 1;
            end
            else
            nr_of_reads <= nr_of_reads - 1;
         end

      Write_Outputs:
         if (M_AXIS_TREADY == 1)
         begin
            if (nr_of_writes == 0)
               state <= Idle;
            else
               nr_of_writes <= nr_of_writes - 1;
         end
      endcase
end

endmodule

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自己塔建AXI STREAM TFT IP核

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