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target_val[1]=0; // initialize to zero
/* enable analog to digital conversion in free run mode
* without noise canceler function. See datasheet of atmega8 page 195
* We set ADPS2=1,ADPS1=0,ADPS0=1 to have a clock division factor of 32.
* This is needed to stay in the recommended range of 50-200kHz
* ADEN: Analog Digital Converter Enable
* ADIE: ADC Interrupt Enable
* ADIF: ADC Interrupt Flag
* ADFR: ADC Free Running Mode
* ADCSR: ADC Control and Status Register
* ADPS2..ADPS0: ADC Prescaler Select Bits
* REFS: Reference Selection Bits (page 203)
*/
// int-ref with external capacitor at AREF pin:
// 2.56V int ref=REFS1=1,REFS0=1
// write only the lower 3 bit for channel selection
// 2.56V ref, start with channel 0
ADMUX=(1<<REFS1)|(1<<REFS0)|(channel & 0x07);
ADCSR=(1<<ADEN)|(1<<ADIE)|(1<<ADFR)|(1<<ADIF)|(1<<ADPS2)|(1<<ADPS0);//32
ADCSR=(1<<ADEN)|(1<<ADIE)|(1<<ADFR)|(1<<ADIF)|(1<<ADPS2)|(1<<ADPS1); //64
可以改改这里试试 |
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